In most modern military electronic systems, the electronic device is typically the warmest element in the system. Although the thermal resistance of many military high-power electronic components can be as large as that of the remaining elements of the system combined, spreaders, heatsinks or coldplates do not directly access the active region where heat is generated, and cannot materially affect the device junction temperature. Since the junction temperature of a power transistor is dominated by the intra-chip heat spreading capability, to lower the device temperature one needs to place materials with high thermal conductivities immediately adjacent to the hot spot of the chip. The conventional GaN HEMT technology (e.g. on SiC, sapphire or Si substrates) suffers from a thermal bottleneck at the chip level. Heat generated from the hot spot in the conventional GaN HEMT will need to go through several microns of poor thermal conductivity GaN epitaxial layer and nucleation layers before reaching the substrate, making devices run hot or and less reliable. The lack of an efficient thermal dissipation pathway results in high device junction temperature, which compromises both performance and reliability.
Known GaN-on-Diamond technology overcomes the thermal bottleneck by applying a high thermal conductivity substrate. Such wafers are formed in a process in which one grows a GaN epitaxial layer on a silicon (Si) substrate. The Si substrate is first removed from the thick GaN epitaxial layer layers (typically ˜2 um) through chemical or mechanical means. A diamond substrate is then applied to the GaN epitaxial layer through very high temperature direct chemical vapor deposition (CVD) growth. The direct growth occurs at high temperatures 600-1000 C. Upon cool-down to room temperature, mismatch in coefficient of thermal expansion (CTE) between GaN and diamond results in significant wafer bow as well as tensile stress in the GaN epitaxial layers. This makes the fabrication of devices and circuits on such a wafer very challenging. The device reliability may also be affected with the extra epitaxial layer stress. The thick GaN epitaxial layer and the GaN to Si transition buffer layers and buffer layers to diamond substrate are significant thermal barriers in the device.
This process results in a number of disadvantages: a) The lower performance of GaN-on-Si as the starting epitaxial layer material results in lower GaN device performance, comparing to that of the industry standard GaN-on-SiC HEMT. b) The large wafer bow makes subsequent device processing difficult. c) High tensile stress in the GaN epitaxial film can lead to reduced device reliability. d) The device does not take the full advantage of the diamond high thermal conductivity due to the thick GaN epitaxial layer and buffer transition layers between the hot spot and the diamond substrate.
Device performance is also inhibited by mechanical stress experienced by the GaN due to wafer bowing.
What is needed therefore is a technique for providing a GaN on Diamond device having improved performance, decreased thermal mismatch, GaN tensile stress, and wafer bow improved use of the diamond wafer thermal conductivity.